QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 120

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

3.8.8.28
120
BCTRL[7:2] - Bridge Control Register
This register provides extensions to the PCICMD register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (that is, PCI
Express) as well as some bits that affect the overall behavior of the “virtual”
PCI-PCI bridge embedded within the MCH, for example, VGA compatible address
range mapping.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:12
7:0
Bit
Bit
11
10
9
RWO
Attr
Attr
RO
RO
RO
RV
0, 2-3
0
3Dh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
3Dh
Intel 5000Z Chipset
4-7
0
3Dh
Intel 5000P Chipset
2-3
0
3Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
3Eh
Intel 5000Z Chipset
4-7
0
3Eh
Intel 5000P Chipset
Default
Default
01h
0h
0
0
0
INTP: Interrupt Pin
This field defines the type of interrupt to generate for the PCI Express port.
001: Generate INTA
010: Generate INTB
011: Generate INTC
100: Generate INTD
Others: Reserved
BIOS/configuration Software has the ability to program this register once
during boot to set up the correct interrupt for the port.
Reserved. (by PCI SIG)
DTSS: Discard Timer SERR Status
Not applicable to PCI Express. This bit is hardwired to 0.
DTS: Discard Timer Status
Not applicable to PCI Express. This bit is hardwired to 0.
SDT: Secondary Discard Timer
Not applicable to PCI Express. This bit is hardwired to 0.
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description