D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 154

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 5 Interrupt Controller
5.4.2
The sources for internal interrupts from on-chip peripheral modules have the following features:
5.5
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. When interrupt control
mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
Rev. 3.00 Mar 17, 2006 page 102 of 926
REJ09B0283-0300
IRQn
input
For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. They can be controlled
independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt
controller.
The interrupt priority level can be set by means of IPR.
The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request.
When the DMAC or DTC is activated by an interrupt request, it is not affected by the interrupt
control mode or CPU interrupt mask bit.
Note: n = 15 to 0
Internal Interrupts
Interrupt Exception Handling Vector Table
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0
IRQnSCA, IRQnSCB
level detection
Edge/
circuit
Clear signal
S
R
IRQnF
Q
IRQnE
IRQn interrupt
request

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