D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 408

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 8 EXDMA Controller
takes back the bus, performs another transfer-unit transfer, and then releases the bus again. This
procedure is repeated until the transfer end condition is satisfied.
If a transfer request occurs in another channel during DMA transfer, the bus is temporarily
released, then transfer is performed on the channel for which the transfer request was issued. If
there is no external space bus request from another bus master, a one-cycle bus release interval is
inserted. For details on the operation when there are requests for a number of channels, see section
8.4.8, Channel Priority Order.
Figure 8.5 shows an example of the timing in cycle steal mode.
Burst Mode: In burst mode, once the EXDMAC acquires the bus it continues transferring data,
without releasing the bus, until the transfer end condition is satisfied. There is no burst mode in
external request mode.
In burst mode, once transfer is started it is not interrupted even if there is a transfer request from
another channel with higher priority. When the burst mode channel finishes its transfer, it releases
the bus in the next cycle in the same way as in cycle steal mode.
When the EDA bit is cleared to 0 in EDMDR, DMA transfer is halted. However, DMA transfer is
executed for all transfer requests generated within the EXDMAC up until the EDA bit was cleared
to 0.
If a repeat area overflow interrupt is generated, the EDA bit is cleared to 0 and transfer is
terminated.
Rev. 3.00 Mar 17, 2006 page 356 of 926
REJ09B0283-0300
EDREQ
EDRAK
Bus cycle
Transfer conditions:
• Single address mode, normal transfer mode
• EDREQ low level sensing
• CPU internal bus master is operating in external space
Figure 8.5 Example of Timing in Cycle Steal Mode
CPU
CPU
EXDMAC
Bus returned temporarily to CPU
CPU
CPU
EXDMAC