D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 33

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Figure 4.4
Section 5 Interrupt Controller
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Figure 5.7
Section 6 Bus Controller (BSC)
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Figure 6.10
Figure 6.11
Figure 6.12
Figure 6.13
Figure 6.14
Figure 6.15
Figure 6.16
Figure 6.17
Figure 6.18
Figure 6.19
Figure 6.20
Figure 6.21
Figure 6.22
Operation when SP Value Is Odd ........................................................................ 83
Block Diagram of Interrupt Controller ................................................................ 86
Block Diagram of Interrupts IRQ15 to IRQ0 ...................................................... 102
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt
Control Mode 0 .................................................................................................... 109
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt
Control Mode 2 .................................................................................................... 111
Interrupt Exception Handling............................................................................... 113
DTC, DMAC, and Interrupt Controller................................................................ 116
Contention between Interrupt Generation and Disabling..................................... 118
Block Diagram of Bus Controller ........................................................................ 122
Read Strobe Negation Timing (Example of 3-State Access Space)..................... 132
CS and Address Assertion Period Extension
(Example of 3-State Access Space and RDNn = 0) ............................................. 134
RAS Signal Assertion Timing
(2-State Column Address Output Cycle, Full Access)......................................... 144
CAS Latency Control Cycle Disable Timing during Continuous Synchronous
DRAM Space Write Access (for CAS Latency 2) ............................................... 148
Area Divisions ..................................................................................................... 153
CSn Signal Output Timing (n = 0 to 7)................................................................ 158
Access Sizes and Data Alignment Control (8-Bit Access Space) ........................ 159
Access Sizes and Data Alignment Control (16-bit Access Space)....................... 159
Bus Timing for 8-Bit, 2-State Access Space........................................................ 161
Bus Timing for 8-Bit, 3-State Access Space........................................................ 162
Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access) ....... 163
Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access)......... 164
Bus Timing for 16-Bit, 2-State Access Space (Word Access)............................. 165
Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access) ....... 166
Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access)......... 167
Bus Timing for 16-Bit, 3-State Access Space (Word Access)............................. 168
Example of Wait State Insertion Timing ............................................................. 170
Example of Read Strobe Timing.......................................................................... 171
Example of Timing when Chip Select Assertion Period Is Extended.................. 172
DRAM Basic Access Timing (RAST = 0, CAST = 0) ........................................ 176
Example of Access Timing with 3-State Column Address Output Cycle
(RAST = 0) .......................................................................................................... 177
Rev. 3.00 Mar 17, 2006 page xxxi of l