D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 727

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Note:
Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
1
0
Bit
7
6
Bit Name
MPB
MPBT
Bit Name
TDRE
RDRF
* Only 0 can be written, to clear the flag.
Initial Value
0
0
Initial Value
1
0
R/W
R
R/W
R/W
R/(W) *
R/(W) *
Section 15 Serial Communication Interface (SCI, IrDA)
Description
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
data. When the RE bit in SCR is cleared to 0 its
previous state is retained.
Multiprocessor Bit Transfer
MPBT sets the multiprocessor bit to be added to
the transmit data.
Description
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
[Clearing conditions]
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
The RDRF flag is not affected and retains their
previous values when the RE bit in SCR is cleared
to 0.
When the TE bit in SCR is 0
When data is transferred from TDR to TSR
When 0 is written to TDRE after reading TDRE
= 1
When the DMAC or DTC is activated by a TXI
interrupt request and transfers data to TDR
When 0 is written to RDRF after reading
RDRF = 1
When the DMAC or DTC is activated by an
RXI interrupt and transferred data from RDR
Rev. 3.00 Mar 17, 2006 page 675 of 926
REJ09B0283-0300

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