D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 36

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

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Figure 6.85
Section 7 DMA Controller (DMAC)
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Rev. 3.00 Mar 17, 2006 page xxxiv of l
Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2) .................. 245
Example of Timing for Idle Cycle Insertion in Case of Consecutive Read
and Write Accesses to DRAM Space in RAS Down Mode................................. 247
Example of Timing for Idle Cycle Insertion in Case of Consecutive Read
and Write Accesses to Continuous Synchronous DRAM Space in RAS Down
Mode (SDWCD = 1, CAS Latency 2) ................................................................. 248
Example of Timing when Write Data Buffer Function is Used........................... 250
Bus Released State Transition Timing................................................................. 253
Bus Release State Transition Timing when Synchronous DRAM Interface........ 254
Block Diagram of DMAC.................................................................................... 260
Areas for Register Re-Setting by DTC (Channel 0A).......................................... 284
Operation in Sequential Mode ............................................................................. 291
Example of Sequential Mode Setting Procedure.................................................. 292
Operation in Idle Mode........................................................................................ 293
Example of Idle Mode Setting Procedure ............................................................ 294
Operation in Repeat mode ................................................................................... 296
Example of Repeat Mode Setting Procedure ....................................................... 297
Operation in Single Address Mode (When Sequential Mode Is Specified) ......... 299
Example of Single Address Mode Setting Procedure
(When Sequential Mode Is Specified) ................................................................. 300
Operation in Normal Mode.................................................................................. 302
Example of Normal Mode Setting Procedure ...................................................... 303
Operation in Block Transfer Mode (BLKDIR = 0).............................................. 305
Operation in Block Transfer Mode (BLKDIR = 1).............................................. 306
Operation Flow in Block Transfer Mode ............................................................. 307
Example of Block Transfer Mode Setting Procedure .......................................... 308
Example of DMA Transfer Bus Timing .............................................................. 309
Example of Short Address Mode Transfer........................................................... 310
Example of Full Address Mode Transfer (Cycle Steal) ....................................... 311
Example of Full Address Mode Transfer (Burst Mode) ...................................... 312
Example of Full Address Mode Transfer (Block Transfer Mode) ....................... 313
Example of DREQ Pin Falling Edge Activated Normal Mode Transfer ............. 314
Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer 315
Example of DREQ Pin Low Level Activated Normal Mode Transfer ................ 316
Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer .... 317
Example of Single Address Mode Transfer (Byte Read)..................................... 318
Example of Single Address Mode (Word Read) Transfer ................................... 319
Example of Single Address Mode Transfer (Byte Write) .................................... 320