D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 287

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space
access following a normal space access, the settings of bits ICIS2 (not available in the H8S/2678
Group), ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in
different areas, for example, if the second read is a full access to DRAM space, only a T
inserted, and a T
In burst access in RAS down mode, the settings of bits ICIS2 (not available in the H8S/2678
Group) , ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. The timing in this case is
illustrated in figures 6.70 and 6.71.
Address bus
CS (area A)
CS (area B)
Figure 6.68 Relationship between Chip Select (CS
RD
Figure 6.69 Example of DRAM Full Access after External Read
Overlap period between CS (area B)
and RD may occur
Address bus
i
cycle is not. The timing in this case is shown in figure 6.69.
(a) No idle cycle insertion
Data bus
T
(ICIS1 = 0)
1
Bus cycle A
RD
T
2
T
3
Bus cycle B
T
T
1
1
External read
T
2
T
(CAST = 0)
2
Address bus
CS (area A)
CS (area B)
T
3
RD
T
p
Rev. 3.00 Mar 17, 2006 page 235 of 926
DRAM space read
T
T
(b) Idle cycle insertion
r
1
Bus cycle A
CS) and Read (RD
CS
CS
(ICIS1 = 1, initial value)
T
Section 6 Bus Controller (BSC)
T
2
c1
T
3
T
Idle cycle
c2
T
i
Bus cycle B
REJ09B0283-0300
RD)
RD
RD
T
1
T
2
p
cycle is