D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 417

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

In burst mode, transfer is halted for up to three DMA transfers following the bus cycle in which 0
is written to the EDA bit. The EDA bit remains set to 1 from the time of the 0-write until the end
of the last DMA cycle.
Writes (except to the EDA bit) are prohibited to registers of a channel for which the EDA bit is set
to 1. When changing register settings after a 0-write to the EDA bit, it is necessary to confirm that
the EDA bit has been cleared to 0.
Figure 8.12 shows the procedure for changing register settings in an operating channel.
BEF Bit in EDMDR: In block transfer mode, the specified number of transfers (equivalent to the
block size) is performed in response to a single transfer request. To ensure that the correct number
of transfers is carried out, a block-size transfer is always executed, except in the event of a reset,
transition to standby mode, or generation of an NMI interrupt.
If an NMI interrupt is generated during block transfer, operation is halted midway through a
block-size transfer and the EDA bit is cleared to 0, terminating the transfer operation. In this case
the BEF bit, which indicates the occurrence of an error during block transfer, is set to 1.
Changing register settings
Figure 8.12 Procedure for Changing Register Settings in Operating Channel
Change register settings
changes completed
in operating channel
Write 0 to EDA bit
Register setting
Read EDA bit
EDA bit = 0?
Yes
No
1
2
3
4
1. Write 0 to the EDA bit in EDMDR.
2. Read the EDA bit.
3. Confirm that EDA = 0. If EDA = 1, this
4. Write the required set values to the
indicates that DMA transfer is in progress.
registers.
Rev. 3.00 Mar 17, 2006 page 365 of 926
Section 8 EXDMA Controller
REJ09B0283-0300