D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 237

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.6.11
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making
consecutive accesses to the same row address. This mode enables fast (burst) access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
Burst Access (Fast Page Mode): Figures 6.30 and 6.31 show the operation timing for burst
access. When there are consecutive access cycles for DRAM space, the CAS signal and column
address output cycles (two states) continue as long as the row address is the same for consecutive
access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in
DRAMCR.
Burst Operation
(Address shift size
set to 10 bits)
This LSI
Figure 6.29 Example of 2-CAS DRAM Connection
RASn (CSn)
HWR (WE)
D15 to D0
RD (OE)
UCAS
LCAS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
Rev. 3.00 Mar 17, 2006 page 185 of 926
1-Mbyte
RAS
UCAS
LCAS
WE
OE
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15 to D0
2-CAS type 16-Mbit DRAM
10-bit column address
Section 6 Bus Controller (BSC)
Row address input:
A9 to A0
Column address input:
A9 to A0
16-bit configuration
REJ09B0283-0300

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