D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 431

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

EDREQ
EDREQ
EDREQ
EDREQ Pin Low Level Activation Timing: Figure 8.27 shows an example of single address
mode transfer activated by the EDREQ pin low level.
EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the single cycle, acceptance resumes and EDREQ pin low
level sampling is performed again; this sequence of operations is repeated until the end of the
transfer.
Figure 8.27 Example of Single Address Mode Transfer Activated by EDREQ
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle is started.
[4], [7] Acceptance is resumed after completion of single cycle.
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held.
(As in [1], EDREQ pin low level is sampled at rise of , and request is held.)
EDREQ
Address bus
EDACK
DMA control
Channel
Idle
[1]
Minimum 3 cycles
Request
Bus release
[2]
clearance period
Single
[3]
Request
DMA single
Transfer source/
destination
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
Rev. 3.00 Mar 17, 2006 page 379 of 926
[5]
clearance period
Single
[6]
Request
DMA single Bus release
Transfer source/
destination
Idle
Section 8 EXDMA Controller
Acceptance
resumed
[7]
EDREQ
EDREQ Pin Low Level
EDREQ
REJ09B0283-0300