D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 447

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

8.5
EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area
overflow interrupts. Table 8.4 shows the interrupt sources and their priority order.
Table 8.4
Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant
channel, and can be sent to the interrupt controller independently. The relative priority order of the
channels is determined by the interrupt controller (see table 8.4).
Figure 8.45 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever
the EDIE bit is set to 1 while the IRF bit is set to 1 in EDMDR.
Interrupt
EXDMTEND0
EXDMTEND1
EXDMTEND2
EXDMTEND3
Interrupt Sources
Interrupt Sources and Priority Order
EDIE bit
IRF bit
Interrupt source
Channel 0 source address repeat area overflow
Channel 0 destination address repeat area overflow
Channel 1 source address repeat area overflow
Channel 1 destination address repeat area overflow
Channel 2 source address repeat area overflow
Channel 2 destination address repeat area overflow
Channel 3 source address repeat area overflow
Channel 3 destination address repeat area overflow
Transfer end indicated by channel 0 transfer counter
Transfer end indicated by channel 1 transfer counter
Transfer end indicated by channel 2 transfer counter
Transfer end indicated by channel 3 transfer counter
Figure 8.45 Transfer End Interrupt Logic
Rev. 3.00 Mar 17, 2006 page 395 of 926
Transfer end interrupt
Section 8 EXDMA Controller
Interrupt Priority
High
Low
REJ09B0283-0300