D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 383

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

7.7.2
When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state
is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is
enabled. This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
7.7.3
When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer
function, dual address transfer external write cycles or single address transfers and internal
accesses (on-chip memory or internal I/O registers) are executed in parallel.
If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
register is read as shown in figure 7.40.
Transfer end/break interrupt (DTE = 0 and DTIE = 1)
TEND pin enable (TEE = 1)
DACK pin enable (FAE = 0 and SAE = 1)
DMA internal
address
DMA control
DMA register
operation
Module Stop
Write Data Buffer Function
Note: The lower word of MAR is the updated value after the operation in [1].
Figure 7.40 Contention between DMAC Register Update and CPU Read
MAR upper
word read
Idle
CPU longword read
[1]
MAR lower
word read
Transfer
source
Read
[2]
Rev. 3.00 Mar 17, 2006 page 331 of 926
DMA read
destination
DMA transfer cycle
Transfer
Write
Section 7 DMA Controller (DMAC)
DMA write
Idle
REJ09B0283-0300