D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 30

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

19.6 On-Board Programming Modes........................................................................................ 788
19.7 Flash Memory Emulation in RAM ................................................................................... 793
19.8 Flash Memory Programming/Erasing ............................................................................... 795
19.9 Program/Erase Protection ................................................................................................. 800
19.10 Programmer Mode ............................................................................................................ 801
19.11 Power-Down States for Flash Memory............................................................................. 801
19.12 Usage Notes ...................................................................................................................... 802
19.13 Note on Switching from F-ZTAT Version to Masked ROM Version .............................. 807
Section 20 Masked ROM
Section 21 Clock Pulse Generator
21.1 Register Descriptions ........................................................................................................ 811
21.2 Oscillator........................................................................................................................... 814
21.3 PLL Circuit ....................................................................................................................... 816
21.4 Frequency Divider ............................................................................................................ 817
21.5 Usage Notes ...................................................................................................................... 817
Section 22 Power-Down Modes
22.1 Register Descriptions ........................................................................................................ 822
Rev. 3.00 Mar 17, 2006 page xxviii of l
19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 781
19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 783
19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 784
19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 785
19.5.5 RAM Emulation Register (RAMER)................................................................... 786
19.6.1 Boot Mode ........................................................................................................... 789
19.6.2 User Program Mode............................................................................................. 792
19.8.1 Program/Program-Verify ..................................................................................... 796
19.8.2 Erase/Erase-Verify............................................................................................... 798
19.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 798
19.9.1 Hardware Protection ............................................................................................ 800
19.9.2 Software Protection.............................................................................................. 800
19.9.3 Error Protection.................................................................................................... 800
21.1.1 System Clock Control Register (SCKCR) ........................................................... 812
21.1.2 PLL Control Register (PLLCR) ........................................................................... 813
21.2.1 Connecting a Crystal Resonator........................................................................... 814
21.2.2 External Clock Input ............................................................................................ 815
21.5.1 Notes on Clock Pulse Generator .......................................................................... 817
21.5.2 Notes on Resonator .............................................................................................. 817
21.5.3 Notes on Board Design ........................................................................................ 818
22.1.1 Standby Control Register (SBYCR) .................................................................... 822
.................................................................................................. 809
...................................................................................... 819
.................................................................................. 811