D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 176

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 6 Bus Controller (BSC)
Name
Chip select 5/row address
strobe 5/SDRAM *
Chip select 6
Chip select 7
Upper column address
strobe/upper data mask
enable
Lower column address
strobe/lower data mask
enable
Output enable/clock
enable
Wait
Bus request
Bus request acknowledge
Bus request output
Data transfer acknowledge
1 (DMAC)
Data transfer acknowledge
0 (DMAC)
Data transfer acknowledge
3 (EXDMAC)
Data transfer acknowledge
2 (EXDMAC)
Rev. 3.00 Mar 17, 2006 page 124 of 926
REJ09B0283-0300
Symbol
CS5/
RAS5/ *
SDRAM *
CS6
CS7
UCAS/
DQMU *
LCAS/
DQML *
OE/CKE *
WAIT
BREQ
BACK
BREQO
DACK1
DACK0
EDACK3
EDACK2
I/O
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Function
Strobe signal indicating that area 5 is selected,
DRAM row address strobe signal when area 5
is DRAM interface space, or dedicated clock
signal for the synchronous DRAM when the
synchronous DRAM interface is selected.
Strobe signal indicating that area 6 is selected.
Strobe signal indicating that area 7 is selected.
16-bit DRAM interface space upper column
address strobe signal, 8-bit DRAM interface
space column address strobe signal, upper
data mask signal of 16-bit synchronous DRAM
interface space, or data mask signal of 8-bit
synchronous DRAM interface space.
16-bit DRAM interface space lower column
address strobe signal or lower data mask signal
for the 16-bit synchronous DRAM interface
space.
Output enable signal for the DRAM interface
space or clock enable signal for the
synchronous DRAM interface space.
Wait request signal when accessing external
space.
Request signal for release of bus to external
bus master.
Acknowledge signal indicating that bus has
been released to external bus master.
External bus request signal used when internal
bus master accesses external address space
when external bus is released.
Data transfer acknowledge signal for single
address transfer by DMAC channel 1.
Data transfer acknowledge signal for single
address transfer by DMAC channel 0.
Data transfer acknowledge signal for single
address transfer by EXDMAC channel 3.
Data transfer acknowledge signal for single
address transfer by EXDMAC channel 2.