D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 780

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 15 Serial Communication Interface (SCI, IrDA)
When turning on the power or switching between Smart Card interface mode and software standby
mode, the following procedures should be followed in order to maintain the clock duty cycle.
Powering On: To secure the clock duty cycle from power-on, the following switching procedure
should be followed.
When changing from smart card interface mode to software standby mode:
Rev. 3.00 Mar 17, 2006 page 728 of 926
REJ09B0283-0300
1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down
2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin
2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive
3. Write 0 to the CKE0 bit in SCR to halt the clock.
4. Wait for one serial clock period.
5. Make the transition to the software standby state.
CKE0
SCK
resistor to fix the potential.
to the value for the fixed output state in software standby mode.
operation. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
During this interval, clock output is fixed at the specified level, with the duty cycle
preserved.
Figure 15.31 Timing for Fixing Clock Output Level
Specified pulse width
Specified pulse width