D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 366
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 DMA Controller (DMAC)
DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA write cycle ends, acceptance
resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
Figure 7.23 shows an example of block transfer mode transfer activated by the DREQ pin falling
edge.
Rev. 3.00 Mar 17, 2006 page 314 of 926
REJ09B0283-0300
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
DREQ
Address
bus
DMA
control
Channel
Figure 7.22 Example of DREQ
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ,
and the request is held.
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.)
Idle
[1]
Request
Bus release
of 2 cycles
Minimum
[2]
Read
[3]
Transfer source
Request clear period
DREQ
DREQ
DREQ Pin Falling Edge Activated Normal Mode Transfer
DMA
read
Write
Transfer destination
Acceptance resumes
DMA
write
Idle
[4]
Request
of 2 cycles
Minimum
release
Bus
[5]
Read
[6]
Transfer source
Request clear period
DMA
read
Write
starts.
Transfer destination
Acceptance resumes
DMA
write
Idle
[7]
release
Bus
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