D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 885
![MCU 3V 0K I-TEMP 144-QFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 885 of 981
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This section gives information on the on-chip I/O registers and is configured as described below.
1. Register Addresses (by functional module, in order of the corresponding section numbers)
2. Register Bits
3. Register States in Each Operating Mode
23.1
Entries under Access size indicates numbers of bits.
Note: Access to undefined or reserved addresses is prohibited. Since operation or continued
Descriptions by functional module, in order of the corresponding section numbers
Entries that consist of
Access to reserved addresses which are not described in this list is prohibited.
When registers consist of 16 or 32 bits, the addresses of the MSBs are given, on the
presumption of a big-endian system.
Bit configurations of the registers are described in the same order as the Register Addresses
(by functional module, in order of the corresponding section numbers).
Reserved bits are indicated by
No entry in the bit-name column indicates that the whole register is allocated as a counter or
for holding data.
When registers consist of 16 or 32 bits, bits are described from the MSB side.
The order in which bytes are described is on the presumption of a big-endian system.
Register states are described in the same order as the Register Addresses (by functional
module, in order of the corresponding section numbers).
For the initial state of each bit, refer to the description of the register in the corresponding
section.
The register states described are for the basic operating modes. If there is a specific reset for an
on-chip module, refer to the section on that on-chip module.
operation is not guaranteed when these registers are accessed, do not attempt such access.
(by functional module, in order of the corresponding section
numbers)
Register Addresses
Section 23 List of Registers
lines are for separation of the functional modules.
in the bit name.
Rev. 3.00 Mar 17, 2006 page 833 of 926
Section 23 List of Registers
REJ09B0283-0300
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