D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 567

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Note:
Note:
Operating
mode
EXPE
CSnE
RMTS2 to
RMTS0
PGnDDR
Pin function PGn
Operating
mode
EXPE
CSnE
PGnDDR
Pin function
PG3/CS3/RAS3 * /CAS * , PG2/CS2/RAS2 * /RAS *
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
PGnDDR, bit CSnE, and bits RMTS2 to RMTS0.
PG1/CS1, PG0/CS0
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
PGnDDR, and bit CSnE.
* Only in H8S/2678R Group.
* Only in H8S/2678R Group.
input
0
0
input
PGn
output
PGn
0
1
0
normal space
input
PGn
output
0
PGn
Area n
1, 2, 4, 5, 6
1
output
CSn
1, 2, 4, 5, 6
1
input
PGn
0
Area n
DRAM
output
space
RASn
1
1
output
CSn
synchro-
DRAM *
1
Area 3
space
output
CAS *
nous
input
PGn
synchro-
DRAM *
Area 2
output
0
space
RAS *
nous
0
output
PGn
input
PGn
1
0
0
output
PGn
input
PGn
1
Rev. 3.00 Mar 17, 2006 page 515 of 926
0
3 * , 7
input
PGn
0
0
output
PGn
0
output
1
PGn
1
1
normal space
input
input
PGn
PGn
0
0
(n =1 or 0)
Area n
3 * , 7
output
1
CSn
1
output
CSn
Section 10 I/O Ports
1
1
REJ09B0283-0300
Area n
DRAM
output
space
RASn
1
synchro-
DRAM *
Area 3
space
output
CAS *
nous
(n = 3 or 2)
synchro-
DRAM *
Area 2
output
space
RAS *
nous

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