D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 729

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Note:
Bit
2
1
0
Bit Name
TEND
MPB
MPBT
* Only 0 can be written, to clear the flag.
Initial Value
1
0
0
R/W
R
R
R/W
Section 15 Serial Communication Interface (SCI, IrDA)
Description
Transmit End
This bit is set to 1 when no error signal has been
sent back from the receiving end and the next
transmit data is ready to be transferred to TDR.
[Setting conditions]
Timing to set this bit differs according to the
register settings.
GM = 0, BLK = 0: 2.5 etu after transmission
GM = 0, BLK = 1: 1.5 etu after transmission
GM = 1, BLK = 0: 1.0 etu after transmission
GM = 1, BLK = 1: 1.0 etu after transmission
[Clearing conditions]
Multiprocessor Bit
This bit is not used in Smart Card interface mode.
Multiprocessor Bit Transfer
Write 0 to this bit in Smart Card interface mode.
When the TE bit in SCR is 0 and the ERS bit
is also 0
If the ERS bit is 0 and the TDRE bit is 1 after
the specified interval after transmission of 1-
byte data
When 0 is written to TEND after reading TEND
= 1
When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR
Rev. 3.00 Mar 17, 2006 page 677 of 926
REJ09B0283-0300