D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 286

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 6 Bus Controller (BSC)
Relationship between Chip Select (CS
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.68. In this case, with the setting for no idle cycle insertion (a), there may be a period of
overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle
insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the
initial state after reset release, idle cycle insertion (b) is set.
Rev. 3.00 Mar 17, 2006 page 234 of 926
REJ09B0283-0300
Address bus
CS (area A)
CS (area B)
HWR, LWR
Data bus
Figure 6.67 Example of Idle Cycle Operation (Read after Write)
RD
(a) No idle cycle insertion
T
(ICIS2 = 0)
1
Bus cycle A
Long output floating time
T
2
T
3
Bus cycle B
T
CS
CS) Signal and Read (RD
CS
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
RD
RD) Signal: Depending on the
RD
T
(b) Idle cycle insertion
1
Bus cycle A
(ICIS2 = 1, initial value)
T
2
T
3
Idle cycle
T
i
Bus cycle B
T
1
T
2