D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 563

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Notes: 1. PG0DDR is initialized to 1 in modes 1, 2, 5, and 6, and to 0 in modes 3, 4, and 7.
Bit
7
6
5
4
3
2
1
0
Bit Name
—
PG6DDR
PG5DDR
PG4DDR
PG3DDR
PG2DDR
PG1DDR
PG0DDR
2. Only in H8S/2678R Group.
Initial Value
0
0
0
0
0
0
0
1/0 *
1
R/W
—
W
W
W
W
W
W
W
Description
Reserved
If read, it returns an undefined value.
Pins PG6 to PG4 function as bus control
input/output pins (BREQO, BACK, and BREQ) when
the appropriate bus controller settings are made.
Otherwise, these pins are I/O ports, and their
functions can be switched with PGDDR.
When the CS output enable bits (CS3E to CS0E)
are set to 1, pins PG3 to PG0 function as CS output
pins when the corresponding PGDDR bit is set to 1,
and as input ports when the bit is cleared to 0.
When CS3E to CS0E are cleared to 0, pins PG3 to
PG0 are I/O ports, and their functions can be
switched with PGDDR.
Pins PG6 to PG4 function as bus control
input/output pins (BREQO, BACK, and BREQ) when
the appropriate bus controller settings are made.
Otherwise, these pins are output ports when the
corresponding PGDDR bit is set to 1, and as input
ports when the bit is cleared to 0.
When the CS output enable bits (CS3E to CS0E)
are set to 1, pins PG3 to PG0 function as CS output
pins when the corresponding PGDDR bit is set to 1,
and as input ports when the bit is cleared to 0.
When CS3E to CS0E are cleared to 0, pins PG3 to
PG0 are I/O ports, and their functions can be
switched with PGDDR.
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Modes 1, 2, 4, 5, and 6
Modes 3 *
Modes 3 *
Rev. 3.00 Mar 17, 2006 page 511 of 926
2
2
, 7 (when EXPE = 1)
, 7 (when EXPE = 0)
Section 10 I/O Ports
REJ09B0283-0300