D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 296

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 6 Bus Controller (BSC)
If a normal space read cycle occurs after a continuous synchronous DRAM space write access
while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The
number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC. It is
not in accordance with the DRMI bit in DRACCR.
Figure 6.80 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
Rev. 3.00 Mar 17, 2006 page 244 of 926
REJ09B0283-0300
Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Precharge-sel
DQMU, DQML
Address bus
Normal space access after a continuous synchronous DRAM space write access
Data bus
CKE
CAS
RAS
WE
RD
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)
PALL ACTV READ
address
Column
T
p
Continuous synchronous
DRAM space read
address
address
Row
Row
T
r
T
Column address 1
c1
T
cl
T
c2
Idle cycle
High
T
i
External space read
External address
External address
T
1
NOP
T
2
T
3
Continuous synchronous
DRAM space read
T
i
Column address 2
T
c1
READ
T
Cl
NOP
T
c2