D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 748

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 15 Serial Communication Interface (SCI, IrDA)
15.4.5
Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
Figure 15.7 shows a sample flowchart for transmission in asynchronous mode.
Rev. 3.00 Mar 17, 2006 page 696 of 926
REJ09B0283-0300
TDRE
TEND
TXI interrupt
request generated
written to TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI)
is generated. Because the TXI interrupt routine writes the next transmit data to TDR before
transmission of the current transmit data has finished, continuous transmission can be enabled.
multiprocessor bit (may be omitted depending on the format), and stop bit.
serial transmission of the next frame is started.
state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
1
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode
Data Transmission (Asynchronous Mode)
Start
bit
0
Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt handling routine
D0
D1
(Example with 8-Bit Data, Parity, One Stop Bit)
1 frame
Data
D7
Parity
bit
0/1
TXI interrupt
request generated
Stop
bit
1
Start
bit
0
D0
D1
Data
D7
Parity
bit
0/1
TEI interrupt
request generated
Stop
bit
1
Idle state
(mark state)
1