SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 107

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P9
(0xFFFF_F031)
P9CR
(0xFFFF_F034)
P9FC
(0xFFFF_F035)
CTS1 /SCLK1 Input Settings
P9FC.P95F
P9CR.P95C
Name
Read/Write
Reset Value
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Note 1:
Note 2:
1
0
Setting bit 0 of the Open-Drain Enable (ODE) register configures theTXD0 pin as an open-drain
output. Setting bit 1 of the ODE register configures the TXD1 pin as an open-drain output. See
Section 7.11.
The P91/RXD0 and P94/RXD1 pins do not have bits for selecting pin functions. These pins can
be continuously used as shared input port and serial data input pins.
Low-speed oscillator consideration
When a low-frequency crystal is connected between XT1 (P96) and XT2 (P97), the following
register settings are required to reduce power consumption:
When a crystal is connected between XT1 and XT2:
When XT1 is driven with an external clock:
TXD1 Output Settings
SCLK1 Output Settings
P9FC.P95F
P9FC.P93F
P9CR.P93C
P9CR.P95C
P9CR.P96C–P97C = 11
P9.P96–P97 = 00
P9CR.P96C–P97C = 11
P9.P96–P97 = 10
P97C
P97
7
7
7
1
1
Output mode
P96C
Figure 7.25 Port 9 Registers
P96
6
6
6
1
1
Port 9 Function Register
Port 9 Control Register
TMP1940CYAF-65
Port 9 Register
0: Port
1: SCLK1
1
1
1
1
0: IN
output or
SCLK1
input
P95C
CTS1 /
P95F
P95
5
5
5
1
0
0
CTS1 /SCLK0 Input Settings
P9FC.P92F
P9CR.P92C
1: OUT
P94C
P94
W
4
4
4
1
0
R/W
W
0: Port
1: TXD1
P93C
P93F
P93
3
3
3
1
0
0
Input mode
0: Port
1: SCLK0
1
0
Port 9 Direction Settings
output or
SCLK0
input
P92C
CTS /
P92F
TMP1940CYAF
P92
2
2
2
1
0
0
1
0
SCLK0 Output Settings
TXD0 Output Settings
P9FC.P90F
P9CR.P90C
P9FC.P92F
P9CR.P92C
0
Output
P91C
Input
P91
1
1
1
1
0
0: Port
1: TXD0
P90C
P90F
P90
0
0
0
1
0
0
1
1
1
1