SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 290
SW00ENB-ZCC
Manufacturer Part Number
SW00ENB-ZCC
Description
MCU, MPU & DSP Development Tools CASEWORKS
Manufacturer
Toshiba
Datasheet
1.SW00ENB-ZCC.pdf
(464 pages)
Specifications of SW00ENB-ZCC
Tool Type
Development Software Support
Core Architecture
870
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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18.4 AC Electrical Characteristics
(1) V CC
No.
10
11
12
13
14
15
16
17
18
19
20
21
* W = 0
W: Number of wait-state cycles inserted (0 to 7 for programmed wait insertion)
N: Value of N for (1 + N) wait insertion
AC measurement conditions:
1
2
3
4
5
6
7
8
9
longer)
System clock period (x)
A0–A15 valid to ALE low
A0–A15 hold after ALE low
ALE pulse width high
ALE low to RD or WR asserted
A0–A15 valid to RD or WR asserted
A0–A23 valid to RD or WR asserted
A0–A23 hold after RD or WR negated
A0–A15 valid to D0–D15 data in
A0–A23 valid to D0–D15 data in
D0–D15 hold after RD negated
D0–D15 valid to WR negated
D0–D15 hold after WR negated
A0–A23 valid to WAIT input
A0–A15 valid to WAIT input
RD or WR negated to ALE high
RD asserted to D0–D15 data in
RD width low
RD negated to next A0–A15 output
WR width low
WAIT hold after RD or WR asserted
Output levels: High = 2.4 V, Low = 0.45 V, CL = 30 pF
Input levels: High = 2 V, Low = 0.6 V
3.0 to 3.6 V, Ta = 0 to 70 C, ALE width
Parameter
TMP1940CYAF-248
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SYS
AL
LA
LL
LC
CL
ACL
ACH
CAR
ADL
ADH
RD
RR
HR
RAE
WW
DW
WD
AWH
AWL
CW
(0.5
x (1
x (1
x (1
0.5 clock cycle (recommended when t
0.4x – 12
0.4x – 8
0.4x – 6
0.4x – 8
x
x
x
x
x
x
31.25
N
Min
W)
W)
W)
0
15
20
20
15
15
15
1) x
Equation
10
10
18
2 (0.5
x (2
x (2
x (1
1.5x
1.5x
33333
Max
N) x
W)
W)
W)
TMP1940CYAF
30
30
42
42
28
17
fsys = 20 MHz *
Min
50
12
14
12
35
30
30
35
40
35
40
32
35
27
8
0
SYS
Max
58
58
22
45
45
58
is 50 ns or
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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