SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 137

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

R/W
Str
31
W
15
0
Bits
31
24
23
22
21
20
19
18
17
16
15
14
13
12
10.3.2
R/W
ExR
30
14
0
Mnemonic
AbIEn
PosE
PosE
NIEn
R/W
ExR
Channel Control Registers (CCRn)
Lev
Big
Str
13
0
R/W
Lev
12
0
Channel Start
Reserved
Normal
Completion
Interrupt Enable
Abnormal
Termination
Interrupt Enable
Reserved
Reserved
Reserved
Reserved
Big-Endian
Reserved
Reserved
External Request
Mode
Positive Edge
Level Mode
Field Name
0
Sreq ReIEN
R/W
11
Figure 10.4 Channel Control Registers (CCRn) (1/2)
0
R/W
10
0
Reset value:
Enables a DMA channel. Setting this bit puts the DMA channel in Ready state. DMA
transfer starts as soon as a transfer request is received.
Only a write of 1 is valid, and a write of 0 has no effect on this bit. A 0 is returned on
read.
1: Enables a DMA channel.
This bit is reserved and must be written as 0.
Reset value = 1
1: Enables an interrupt when the channel finishes a transfer without an error condition.
0: Does not enable an interrupt when the channel finishes a transfer without an error
Reset value = 1
1: Enables an interrupt when the channel encounters a transfer error.
0: Does not enable an interrupt when the channel encounters a transfer error.
This bit is reserved and must be written as 0.
This bit is reserved and must be written as 0.
This bit is reserved and must be written as 0.
This bit is reserved and must be written as 0.
Reset value = 1
1: The DMA channel operates in big-endian mode.
0: The DMA channel operates in little-endian mode.
In the TMP1940CYAF, this bit must be cleared to 0.
This bit is reserved and must be written as 0.
This bit is reserved and must be written as 0.
Reset value = 0
Selects a transfer request mode.
1: External transfer requests (interrupt-driven)
0: Internal transfer requests (software-initiated)
Reset value = 0
Defines the polarity of the internal DMA request signal (INTDREQn) for the channel.
This bit is valid for external transfer requests (i.e., when ExR=1), and has no effect on
internal transfer requests (i.e., when ExR=0).
In the TMP1940CYAF, the PosE bit must be cleared, and the Lev bit must be set.
Reset value = 0
Specifies whether external transfer requests are level-senstiive or edge-triggered.
This bit is valid for external transfer requests (i.e., when ExR=1), and has no effect on
internal transfer requests (i.e., when ExR=0).
In the TMP1940CYAF, this bit must be set.
R/W
SIO
25
9
0
condition.
TMP1940CYAF-95
24
W
8
SAC
R/W
00
NIEn
R/W
23
1
7
AblEn
R/W
R/W
DIO
22
1
6
0
R/W
21
1
5
Description
DAC
R/W
00
R/W
20
0
4
R/W
19
0
3
TMP1940CYAF
TrSiz
R/W
00
R/W
18
0
2
R/W
Big
17
1
1
DPS
R/W
00
R/W : Read/Write
16
0
0
: Reset Value
: Reset Value
: Read/Write