SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 281

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2
When a counter overflow occurs, the WDT generates a WDT interrupt, as shown below.
programmed, a counter overflow causes the WDT to assert the internal reset signal for a 22- to 29-state time.
After a reset, the fsys clock is, by default, generated by dividing the high-speed oscillator clock (fc) by eight
through the clock gear function; the WDT clock source (fsys/2) is derived from this fsys clock.
15
The WDT contains a 22-stage binary counter clocked by the fsys/2 clock. This binary counter provides
Also, the counter overflow can be programmed to cause a system reset as the time-out action. If so
, 2
Note:
WDT Interrupt
Internal Reset
WDT Counter
WDT Interrupt
WDT Counter
(via software)
17
WDT Clear
, 2
19
The TMP1940CYAF continues sampling the PLLOFF pin during a reset operation caused by the WDT.
Therefore, the PLLOFF pin must be tied to either logic high or logic low.
or 2
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as a counter overflow signal, as programmed into the WDTP[1:0] field in the WDMOD.
n
n
Figure 16.3 Reset Operation
22–29 States (11–14.5 s @ fc
TMP1940CYAF-239
Overflow
Figure 16.2 Default Operation
Overflow
A write of a special clear-count code
32 MHz, fsys
4 MHz, fsys/2
TMP1940CYAF
2 MHz)
0