SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 160

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SYSCR1.FPSEL
Peripheral Clock
Note 1: The prescaler's output clock Tn must be selected so that Tn < fsys/2 is satisfied.
Note 2: Do not change the clock gear value while the timer is running.
Note 3: The — character means “Don’t use.”
11.2 Timer Components
11.2.1
0 (fgear)
Select
1 (fc)
Prescaler
prescalar clock source ( T0 can be selected from fperiph, fperiph/2 and fperiph/4 by programming the
PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared
clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG.
the TMRA01. A write of 1 to this bit starts the prescalar. A write of 0 to this bit clears and halts the
prescalar.
by-512 ( T256). Table 11.2 shows prescalar output clock resolutions (@fc = 32 MHz).
The TMRA01 has a 9-bit prescalar that slows the rate of a clocking source to the counters. The
The TA01PRUN bit in the TA01RUN register allows the enabling and disabling of the prescalar for
Prescalar output taps can be divide-by-2 (
SYSCR1.GEAR[1:0]
Clock Gear Value
01 (fc/2)
10 (fc/4)
11 (fc/8)
01 (fc/2)
10 (fc/4)
11 (fc/8)
00 (fc)
00 (fc)
Table 11.2 Prescalar Output Clock Resolutions
SYSCR0.PRCK[1:0]
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
Prescaler Clock
TMP1940CYAF-118
Source
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
, divide-by-8 ( T4), divide-by-32 ( T16) and divide-
3
2
4
3
5
4
6
5
3
2
3
(0.25 s)
(0.125 s) fc/2
(0.5 s)
(0.25 s)
(1.0 s)
(0.5 s)
(2.0 s)
(1.0 s)
(0.25 s)
(0.125 s) fc/2
(0.25 s)
T1
Prescalar Output Clock Resolution
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
5
4
3
6
5
4
7
6
5
8
7
6
5
4
3
5
4
3
5
4
5
(1.0 s)
(0.5 s)
(0.25 s) fc/2
(2.0 s)
(1.0 s)
(0.5 s)
(4.0 s)
(2.0 s)
(1.0 s)
(8.0 s)
(4.0 s)
(2.0 s)
(1.0 s)
(0.5 s)
(0.25 s) fc/2
(1.0 s)
(0.5 s)
(0.25 s) fc/2
(1.0 s)
(0.5 s)
(1.0 s)
T4
TMP1940CYAF
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
7
6
5
8
7
6
9
8
7
10
9
8
7
6
5
7
6
5
7
6
5
7
6
5
T16
(4.0 s) fc/2
(2.0 s) fc/2
(1.0 s) fc/2
(8.0 s) fc/2
(4.0 s) fc/2
(2.0 s) fc/2
(16 s) fc/2
(8.0 s) fc/2
(4.0 s) fc/2
(16 s) fc/2
(8.0 s) fc/2
(4.0 s) fc/2
(2.0 s) fc/2
(1.0 s) fc/2
(4.0 s) fc/2
(2.0 s) fc/2
(1.0 s) fc/2
(4.0 s) fc/2
(2.0 s) fc/2
(1.0 s) fc/2
(4.0 s) fc/2
(2.0 s) fc/2
(1.0 s) fc/2
(32 s) fc/2
@fc
11
10
9
11
10
9
11
10
9
11
10
9
11
10
9
12
11
10
13
12
11
14
13
12
T256
(16 s)
(16 s)
(16 s)
(16 s)
(16 s)
(64 s)
(32 s)
(128 s)
(64 s)
(32 s)
(256 s)
(128 s)
(64 s)
(512 s)
(256 s)
(128 s)
(64 s)
(32 s)
(64 s)
(32 s)
(64 s)
(32 s)
(64 s)
(32 s)
32MHz