SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 135

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3 Register Description
The DMAC has twenty-six 32-bit registers. The DMAC register map is shown in Table 10.1.
0xFFFF_E200
0xFFFF_E204
0xFFFF_E208
0xFFFF_E20C
0xFFFF_E210
0xFFFF_E218
0xFFFF_E220
0xFFFF_E224
0xFFFF_E228
0xFFFF_E22C
0xFFFF_E230
0xFFFF_E238
0xFFFF_E240
0xFFFF_E244
0xFFFF_E248
0xFFFF_E24C
0xFFFF_E250
0xFFFF_E258
0xFFFF_E260
0xFFFF_E264
0xFFFF_E268
0xFFFF_E26C
0xFFFF_E270
0xFFFF_E278
0xFFFF_E280
0xFFFF_E28C
Address
Symbol
DTCR0
DTCR1
DTCR2
DTCR3
CCR0
CSR0
BCR0
CCR1
CSR1
BCR1
CCR2
CSR2
BCR2
CCR3
CSR3
BCR3
SAR0
DAR0
SAR1
DAR1
SAR2
DAR2
SAR3
DAR3
DCR
DHR
Table 10.1 DMAC Registers
TMP1940CYAF-93
Channel Control Register (Ch. 0)
Channel Status Register (Ch. 0)
Source Address Register (Ch. 0)
Destination Address Register (Ch. 0)
Byte Count Register (Ch. 0)
DMA Transfer Control Register (Ch. 0)
Channel Control Register (Ch. 1)
Channel Status Register (Ch. 1)
Source Address Register (Ch. 1)
Destination Address Register (Ch. 1)
Byte Count Register (Ch. 1)
DMA Transfer Control Register (Ch. 1)
Channel Control Register (Ch. 2)
Channel Status Register (Ch. 2)
Source Address Register (Ch. 2)
Destination Address Register (Ch. 2)
Byte Count Register (Ch. 2)
DMA Transfer Control Register (Ch. 2)
Channel Control Register (Ch. 3)
Channel Status Register (Ch. 3)
Source Address Register (Ch. 3)
Destination Address Register (ch. 3)
Byte Count Register (Ch. 3)
DMA Transfer Control Register (Ch. 3)
DMA Control Register (All channels)
Data Holding Register (All channels)
Register Name
TMP1940CYAF