SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 396

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.5.8
RAM Transfer Command
(1) The 1st byte specifies which one of the two serial operation modes is used. For a detailed
(2) The 2nd byte, transmitted from the target board to the controller, is an acknowledge response to
See Table 3.6.
description of how the serial operation mode is determined, see Section 3.5.12. If it is determined
as UART mode, the boot program then checks if the SIO0 is programmable to the baud rate at
which the 1st byte was transferred. During the first-byte interval, the RXE bit in the SC0MOD0
register is cleared.
the 1st byte. The boot program echoes back the first byte : 86H for UART mode and 30H for I/O
Interface mode.
Before initiating a transfer, the RAM Transfer command checks a password sequence coming
from the controller against that stored in the flash memory. If they do not match, the RAM
Transfer command aborts.
Once the RAM Transfer command is complete, the whole on-chip RAM is accessible.
Show Flash Memory Sum command
The Show Flash Memory Sum command adds the contents of the 512 Kbytes of the flash
memory together. The boot program does not provide a command to read out the contents of
the flash memory. Instead, the Flash Memory Sum command can be used for software revision
management.
Show Product Information command
The Show Product Information command provides the product name, on-chip memory
configuration and the like. This command also reads out the contents of the flash memory
locations at addresses 0x0000_03F0 through 0x0000_03F3. In addition to the Show Flash
Memory Sum command, these locations can be used for software revision management.
To communicate in UART mode
Send, from the controller to the target board, 86H in UART data format at the desired baud
rate. If the serial operation mode is determined as UART, then the boot program checks if the
SIO0 can be programmed to the baud rate at which the first byte was transferred. If that baud
rate is not possible, the boot program aborts, disabling any subsequent communications.
To communicate in I/O Interface mode
Send, from the controller to the target board, 30H in I/O Interface data format at 1/16 of the
desired baud rate. Also send the 2nd byte at the same baud rate. Then send all subsequent bytes
at a rate equal to the desired baud rate.
In I/O Interface mode, the CPU sees the serial receive pin as if it were a general input port in
monitoring its logic transitions. If the baud rate of the incoming data is high or the chip’s
operating frequency is low, the CPU may not be able to keep up with the speed of logic
transitions. To prevent such situations, the 1st and 2nd bytes must be transferred at 1/16 of the
desired baud rate; then the boot program calculates 16 times that as the desired baud rate.
When the serial operation mode is determined as I/O Interface mode, the SIO0 is configured
for SCLK Input mode. Beginning with the third byte, the controller must ensure that its AC
timing restrictions are satisfied at the selected baud rate. In the case of I/O Interface mode, the
boot program does not check the receive error flag; thus there is no such thing as error
acknowledge (x8H).
TMP1940FDBF-38
TMP1940FDBF