SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 255

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTS2 Interrupt
INTS2 Interrupt
Write to SBI0DBR
Figure 14.14 SBI0CR1.BC[2:0] = 000 and SBI0CR1.ACK = 1 (Master-Transmitter Mode)
Request
SDA Pin
SCL Pin
Request
Figure 14.15 SBI0CR1.BC[2:0] = 000 and SBI0CR1.ACK = 1 (Master-Receiver Mode)
PIN Bit
PIN Bit
SDA
SCL
Master-Receiver Mode (SBI0CR2.TRX = 0)
program the BC[2:0] and ACK bits in the SBI0CR1, and then read the SBI0DBR. The first read of
the SBI0DBR is a dummy read because data has not yet been received. A dummy read returns an
undefined value. Upon this read, the SCL line is released, the PIN bit in the SBI0SR is set, and the
SCL clock is driven out to receive a data word into the SBI0DBR. The master-transmitter
generates an acknowledgement signal (i.e., a low level) on the SDA line following the last received
bit.
SBI0CR1 immediately before the read of the second to last data word. This causes an
acknowledge clock pulse not to be generated on the last data word.
INTS2 interrupt handler must set the BC[2:0] field in the SBI0CR1 to 001 and read the SBI0DBR,
INTS2 interrupt
if MST = 0
Then go to slave-mode processing
if TRX = 0
Then go to receiver-mode processing
if LRB = 0
Then go to processing for generating a STOP condition
SBI0DBR
SBI0DBR
End of interrupt processing
X = Don’t care
If the number of bits per transfer is 8, read the SBI0DBR. When using other data length,
To prepare to terminate the data transfer, the master-receiver must clear the ACK bit in the
When the transfer is complete, the INTS2 interrupt is generated. After interrupt processing, the
Read of the received data.
D7
D7
1
1
X X X X X X X X
D6
D6
2
2
D5
D5
TMP1940CYAF-213
3
3
D4
D4
4
4
Set number of bits to be transmitted and specify whether
ACK is required.
Load the transmit data.
D3
D3
5
5
D2
D2
6
6
D1
D1
7
7
TMP1940CYAF
D0
D0
8
8
Master to Slave
Slave to Master
ACK
Master to Slave
Slave to Master
ACK
9
9
Acknowledgement
signal to transmitter
Acknowledgement
signal from receiver
Next D7