SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 116

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2
8.2.1
External Bus Operation
address bus, and AD15–AD0 is the address/data bus.
Characteristics, for detailed timing specifications.
This section describes external bus operations. In the timing diagrams which follow, A23–A16 is the
This section only provides a functional description of the bus; refer to Section 18, AC Electrical
Basic Bus Operation
allows the bus cycle to be extended by inserting wait states.
chip address is being accessed, the external address bus maintains the previous value with the ALE pin
kept inactive. During this time, the address/data bus assumes the high-impedance state, and bus control
signals such as RD and WR remain inactive.
While the TMP1940CYAF provides a total of three clock cycles to perform a read or write, it also
Figure 8.1 shows external bus read timing. Figure 8.2 shows external bus write timing. While an on-
Note: tsys is the system clock period.
A[23:16]
AD[15:0]
ALE
A[23:16]
AD[15:0]
ALE
WR
RD
tsys
tsys
Figure 8.1 Read Cycle Timing
Figure 8.2 Write Cycle Timing
ADR
ADR
TMP1940CYAF-74
External access
External access
DATA
DATA
Internal access
Internal access
Inactive
No change
Inactive
Inactive
Inactive
No change
Hi-Z
Hi-Z
TMP1940CYAF