SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 411

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.6.4
3.6.5
3.6.6
3.6.7
Read Mode and Embedded Operation Mode
Read mode. In Embedded Operation mode, array data can not be read.
Reading Array Data
and after an embedded operation is successfully completed.
Writing Commands
internal command register. This uses the same mechanism as for JEDEC-standard EEPROMs.
Commands are made up of data sequences written at specific addresses via the command register. See
Table 3.16 on page 60 for the list of command sequences.
sequence, the fourth (write) cycle in the Auto Program command sequence and the fourth (write) cycle
in the Verify Block Protect command sequence. Thus commands can be provided byte by byte.
sequence cycles. The Read/Reset command clears the command register and resets the flash memory to
Read mode. Invalid command sequences also cause the flash memory to clear the command register and
return to Read mode.
Reset
The flash memory of the TMP1940FDBF has the following two modes of operation:
The flash memory enters Embedded Operation mode when a valid command sequence is executed in
The flash memory is automatically set to reading array data upon CPU reset after device power-up
The operations of the flash memory are selected by commands or command sequences written into the
Commands are written via DQ0–DQ7 except the fourth (read) cycle in the Read/Reset command
The command sequence being written can be canceled by issuing the Read/Reset command between
Read mode in which array data is read
Embedded Operation mode in which the flash array is programmed or erased
Read/Reset command (software reset)
The flash memory does not return to Read mode if an embedded operation terminated
abnormally. In this case, the Read/Reset command must be issued to put the flash memory back
in Read mode. The Read/Reset command may also be written between sequence cycles of the
command being written to clear the command register.
Hardware reset (
As shown in Figure 3.17, the flash memory has a reset pin, which is connected to the reset
signal of the CPU. When the system drives the
as a watchdog timer time-out causes a CPU reset, the flash memory immediately terminates any
operation in progress and is reset to Read mode.
The Read/Reset command is also tied to the
mode. The embedded operation that was interrupted should be re-initiated once the flash
memory is ready to accept another command sequence because data may be corrupted.
For a description of the hardware reset operation, see Section 3.3.2, Reset Operation. When a
valid reset is achieved, the CPU reads the Reset exception vector from the flash memory and
services the Reset exception.
RESET
TMP1940FDBF-53
input)
RESET
RESET
pin to reset the flash memory to Read
pin to V
TMP1940FDBF
IL
or when certain events such