SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 242

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.2 Registers
14.3 I
2
C Bus Mode Data Formats
A listing of the registers used to control the SBI follows:
Figure 14.2 shows the serial bus interface data formats used in I
(a) Addressing format
(b) Addressing format (with repeated START condition)
(c) Free data format (master-transmitter to slave-receiver)
S = START condition
R/ W = Direction bit
ACK = Acknowledge bit
P = STOP condition
Serial Bus Interface Control Register 1 (SBI0CR1)
Serial Bus Interface Control Register 2 (SBI0CR2)
Serial Bus Interface Data Buffer Register (SBI0DBR)
I
Serial Bus Interface Status Register (SBI0SR)
Serial Bus Interface Baud Rate Register 0 (SBI0BR0)
Serial Bus Interface Baud Rate Register 1 (SBI0BR1)
detailed description of the registers, refer to Section 14.5, I
14.8, Clock-Synchronous 8-Bit SIO Mode Operation.
2
C Bus Address Register (I2C0AR)
The functions of these registers vary, depending on the mode in which the SBI is operating. For a
S
S
S
Slave address
Slave address
8 bits
8 bits
8 bits
Data
Once
Once
Once
Figure 14.2 I
W
W
R
R
/
/
C
C
C
1
A
K
1
A
K
1
A
K
TMP1940CYAF-200
1 to 8 bits
1 to 8 bits
1 to 8 bits
2
Repeated
C-Bus Mode Data Formats
Data
Data
Data
Repeated
Repeated
C
C
C
A
K
A
K
A
K
1
1
1
S
Slave address
1 to 8 bits
1 to 8 bits
Data
Data
2
8 bits
2
C Bus mode.
C Bus Mode Configuration, and Section
Once
A
C
K
R
W
A
C
K
1
1
/
TMP1940CYAF
C
P
A
K
P
1
1 to 8 bits
Repeated
Data
A
C
K
1
P