SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 150

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4.4
Note:
the write cycle takes two bus cycles.) The 32 bits of data are buffered in the DHR until the destination
write cycle occurs.
The SARn and DARn change, if so programmed, after each data transfer, depending on the transfer
size, i.e., the programmed TrSiz value. The BRCn is decremented by TrSiz for each data transfer.
(TrSiz).
DMA Channel Operation
the channel setups for configuration errors. If no configuration error is present, the channel enters
Ready state.
transferring data.
(1) Channel Startup
(2) Channel Termination
Table 10.2 DMA Transfer Sizes and Device Port Sizes (in Dual-Address Mode)
Source and destination addresses can be programmed to increment or decrement after each transfer.
It is forbidden to program the device port size (DPS) to a value greater than the DMA transfer size
The relationships between TrSiz and DPS are summarized below.
Each DMA channel is started by setting the Str bit in the CCRn to 1. Once started, the DMAC checks
When a DMA request is detected while in Ready state, the DMAC arbitrates for the bus and begins
The channel can terminate by normal completion or from an error.
error is detected, the channel terminates abnormally. If no configuration error is present, the
channel enters Ready state. Once a channel enters Ready state, the Act bit in the CSRn is set to 1.
transferring data immediately. If the channel is programmed for external request, INTDREQn must
be asserted before the channel requests the bus.
operation can be determined by reading the CSRn.
the NC or AbC bit in the CSRn is set.
The DMAC does not incremnt or decrement the address for I/O peripherals. Therefore, if, for
example, TrSiz is programmed to 16 bits and DPS is programmed to 8 bits, both the first and second
bus cycles access the lower eight bits of the I/O data bus.
A DMA channel is started by setting the Str bit in the CCRn.
Once started, the DMAC checks the channel setups for configuration errors. If a configuration
If the channel is programmed for internal request, the channel requests the bus and starts
A DMA channel can terminate by normal completion or from an error. The status of a DMA
A channel terminates abnormally when an attempt is made to set the Str bit in the CCRn when
0x (32 bits)
0x (32 bits)
0x (32 bits)
10 (16 bits)
10 (16 bits)
10 (16 bits)
11 (8 bits)
11 (8 bits)
11 (8 bits)
TrSiz
0x (32 bits)
10 (16 bits)
11 (8 bits)
0x (32 bits)
10 (16 bits)
11 (8 bits)
0x (32 bits)
10 (16 bits)
11 (8 bits)
TMP1940CYAF-108
DPS
# of I/O Bus Cycles
Don’t use.
Don’t use.
Don’t use.
1
2
4
1
2
1
TMP1940CYAF