SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 398

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(7) The 18th byte, transmitted from the target board to the controller, is an acknowledge response to
(8) The 19th to 22nd bytes, which the target board receives from the controller, indicate the start
(9) The 23rd and 24th bytes, which the target board receives from the controller, indicate the number
(10) The 25th byte is a checksum value for the 19th to 24th bytes. To calculate the checksum value, add
(11) The 26th byte, transmitted from the target board to the controller, is an acknowledge response to
the 5th to 17th bytes.
First, the RAM Transfer routine checks for a receive error in the 5th to 17th bytes. If there was a
receive error, the boot program sends back 18H and returns to the state in which it waits for a
command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response
are the same as those of the previously issued command (i.e., all 1s). When the SIO0 is configured
for I/O Interface mode, the RAM Transfer routine does not check for a receive error.
Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding
the series of the 5th to 17th bytes must result in zero (with the carry dropped). If it is not zero, one
or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine
sends back 11H to the controller and returns to the state in which it waits for a command (i.e., the
3rd byte) again.
Finally, the RAM Transfer routine examines the result of the password check. The following two
cases are treated as a password error. In these cases, the RAM Transfer routine sends back 11H to
the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again.
When all the above checks have been successful, the RAM Transfer routine returns a normal
acknowledge response (10H) to the controller.
address of the RAM region where subsequent data (e.g., a flash programming routine) should be
stored. The 19th byte corresponds to bits 31–24 of the address, and the 22nd byte corresponds to
bits 7–0 of the address.
of bytes that will be transferred from the controller to be stored in the RAM.
all these bytes together, drop the carries and take the two’s complement of the total sum. Transmit
this checksum value from the controller to the target board. The checksum calculation is described
in details in Section 3.5.15.
the 19th to 25th bytes of data.
First, the RAM Transfer routine checks for a receive error in the 19th to 25th bytes. If there was a
receive error, the RAM Transfer routine sends back 18H and returns to the state in which it waits
for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge
response are the same as those of the previously issued command (i.e., all 1s). When the SIO0 is
configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error.
Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding
the series of the 19th to 25th bytes must result in zero (with the carry dropped). If it is not zero,
one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer
routine sends back 11H to the controller and returns to the state in which it waits for a command
(i.e., the 3rd byte) again.
Irrespective of the result of the password comparison, all of the 12 bytes of a password in the
flash memory are the same value other than FFH.
Not all of the password bytes transmitted from the controller matched those contained in the
flash memory.
TMP1940FDBF-40
TMP1940FDBF