SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 390

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.5.5
Interface Specification
Both UART (asynchronous) and I/O Interface (synchronous) modes are supported. The communication
formats are shown below. In the subsections that follow, virtual addresses are indicated, unless
otherwise noted.
program clears the RXE bit in the SC0MOD0 register, disabling data reception via the SIO0.
The following enumerates the steps for the TMP1940FDBF to receive and transmit data from/to a host
controller.
(1) As shown in Figure 3.10, set the RXE bit in the SC0MOD0 register to enable reception and bring
(2) When the SIO0 has received a byte of data, the SC0MOD0.RXE bit is automatically cleared to
(3) The controller must perform the next action after a high-to-low transition occurs on P76.
In Single Boot mode, an SIO channel is used for communications with a programming controller.
Power Supply Pins
Mode-Setting Pin
Reset Pin
Communications
Pins
I/O Interface mode uses a simple handshaking protocol, which is shown in Figure 3.10. The boot
The host controller must communicate with the TMP1940FDBF, using the P76 pin for handshaking.
For receive:
the P76 pin high to inform the controller that the TMP1940FDBF is ready to communicate. Then,
wait for the SCLK0 signal to come from the controller.
disable reception until the data is picked up by the CPU and the receive interrupt request is
cleared. At this time, bring P76 low to indicate to the controller that the TMP1940FDBF is not
ready to receive or transmit the next byte. When the TMP1940FDBF is ready and if the next action
of the boot program is again a reception, set the SC0MOD0.RXE bit, bring P76 high and wait for
an active SCLK0 edge to come from the controller.
UART mode
I/O Interface mode
Communications channel: SIO Channel 0 (SIO0)
Transfer mode:
Data length:
Parity bits:
STOP bits:
Baud rate:
Communications channel:
Transfer mode:
Synchronization clock (SCLK0): Input
Handshaking signal:
Baud rate:
Pin
Table 3.4 Required Pin Connections
DVCC (3.3 V)
DVSS
TXD0
RXD0
SCLK0
P76
BOOT
RESET
TMP1940FDBF-32
UART (asynchronous) mode, full-duplex
8 bits
None
1
See Table 3.13 on page 50.
UART Mode
Not Required
Not Required
SIO Channel 0 (SIO0)
I/O Interface mode, half-duplex
P76 configured as an output
See Table 3.13 on page 50.
Required
Required
Required
Required
Required
Required
Interface
I/O Interface Mode
Required (Input Mode)
Required (Input Mode)
Required
Required
Required
Required
Required
Required
TMP1940FDBF