SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 174

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the duty cycle) can be changed dynamically by writing a new value into the register buffer. Upon a 2
counter overflow, the TA0REG latches a new value from the register buffer.
signal with variable duty cycle.
In 8-bit PWM generation mode, if the double-buffering function is enabled, the TA0REG value (i.e.,
The TA0REG can be loaded with a new value upon every counter overflow, thus generating a PWM
Example: Generating a PWM signal as shown below on the TA1OUT pin (fc = 32 MHz)
X = Don’t care,
Match Between TA0REG
TA01RUN
TA01MOD
TA0REG
TA1FFCR
P7CR
P7FC
TA01RUN
Clocking conditions:
Under the above conditions, T1 has a 0.25-µs period (@fc = 32 MHz).
which is equal to 2
Hence, the time constant value to be programmed into the TA0REG is 48H.
System clock:
High-speed clock gear: ×1 (fc)
Prescaler clock:
and Up-Counter 0
31.75 s
18 s
(Compare Value)
Register Buffer
2
n
-1 Overflow
MSB
TA0REG
0.25 s
– = No change
7
1
0
X
1
0.25 s
Figure11.17 Register Buffer Operation
6
X
1
1
X
X
18 s
31.75 s
7
– 1.
5
X
1
0
X
X
72
TMP1940CYAF-132
127
4
X
0
0
X
X
48H
Up-Counter
High-speed (fc)
fperiph/4 (fperiph = fsys)
3
1
1
2
0
0
1
Q
Q
1
0
0
1
1
1
1
2
LSB
0
0
1
0
X
1
Q
1
Stops and clears the TMRA0.
Selects 8-bit PWM mode (period = 2
the clock source.
Writes 48H.
Clears the TA1FF to 0 and enables toggling.
Configures P71 as the TA1OUT output pin.
Starts the TMRA0.
Shift into TA0REG
Up-Counter
TMP1940CYAF
Q
Write to TA0REG
(Register Buffer)
2
Q
2
Q
3
7
1) and T1 as
n
-1