SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 253

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.6 Programming Sequences in I
14.6.1
14.6.2
SBI Initialization
the SBI0BR1.P4EN bit to 1 to enable the internal baud rate generation logic. Write 0s to bits 7–5 and
bit 3 in the SBI0CR1.
the ALS bit (bit 0) selects an address recognition mode. (The ALS bit must be cleared when using the
addressing format.)
TRX and BB bits to 0, set the PIN bit to 1 and set the SBIM[1:0] field to 10. Write 00 to the
SWRST[1:0] field.
Generating a START Condition and a Slave Address
(1) Master Mode
First, program the P4EN bit in the SBI0BR1, and the ACK and SCK[2:0] bits in the SBI0CR1. Set
Next, program the I2C0AR. The SA[6:0] field in the I2C0AR defines the chip’s slave address, and
Next, program the SBI0CR2 to initially configure the SBI in slave-receiver mode; i.e., clear the MST,
address on the I
loads the SBI0DBR with a slave address and a data direction bit to be transmitted via the I
condition to be generated on the bus. Following a START condition, the SBI generates SCL clock
pulses nine times: the SBI shifts out the contents of the SBI0DBR with the first eight SCL clocks,
and releases the SDA line during the last (i.e., ninth) SCL clock to receive an acknowledgement
signal from the addressed slave.
the PIN bit in the SBI0CR2 is cleared to 0. In master mode, the SBI holds the SCL line low while
the PIN bit is 0. Upon interrupt, the TRX bit either remains set or is cleared according to the value
of the transmitted direction bit, provided an acknowledgement signal has been returned from the
slave.
SBI0BR1
SBI0CR1
I2C0AR
SBI0CR2
Settings in main routine
Reg.
Reg.
if Reg.
Then
SBI0CR1
SBI0DBR
SBI0CR2
INTS2 interrupt routine
INTCLR
Interrupt processing
End of interrupt
Note: X = Don’t care
In master mode, the following steps are required to generate a START condition and a slave
First, ensure that the bus is free (i.e., SBI0CR2.BB = 0).
Next, set the ACK bit in the SBI0CR1 to enable generation of acknowledge clock pulses. Then,
When BB=0, writing 1s to the MST, TRX, BB and PIN bits in the SBI0CR2 causes a START
The INTS2 interrupt request is generated on the falling edge of the ninth SCL clock pulse, and
0x00
2
7 6 5 4 3 2 1 0
X X X 1 0 X X X
X X X X X X X X
1 1 1 1 1 0 0 0
7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0
0 0 0 X 0 X X X
X X X X X X X X
0 0 0 1 1 0 0 0
SBI0SR
Reg. & 0x20
0x34
C-bus.
TMP1940CYAF-211
2
C Bus Mode
Enable internal baud rate generator.
Disable generation of ACK and select SCL clock frequency.
Load a slave address and selects address recognition mode.
Configure the SBI in slave-receiver mode.
Ensure that the bus is free.
Select Acknowledgement mode.
Load the slave address and a data direction bit.
Generate a START condition.
Clear the interrupt request.
TMP1940CYAF
2
C bus.