SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 438

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.7.17
Flash Security
security bit disables access to the flash array. This prevents intrusive access to the flash memory by third
parties while in Programmer mode.
The TMP1940FDBF flash memory has a security bit apart from the flash array. Programming this
flash memory is ready to accept the next command. If any failure occurs during the program or
erase operation, this flag remains at the 0 logic state. Any command is ignored while
RDY_BSY is at the 0 logic state. RDY_BSY is not a open-drain output pin, but a normal
CMOS output pin.
Securing the flash (Disabling read accesses)
Securing the flash memory disables programming equipment to read its contents. To turn on the
security feature, once programming is complete, write the Auto Security On command, with the
FSE pin set to V
address 0x0000. After the rising edge of
On algorithm automatically programs and verifies the security bit.
Any commands written during the embedded operation are ignored. A hardware reset
immediately terminates the embedded operation. The FSE pin must be held stable throughout
the embedded operation.
When the embedded algorithm completes, the flash memory automatically returns to Read
mode.
If any failure occurs during the embedded operation, the flash memory remains locked in
Embedded Operation mode and does not return to Read mode. The system can determine the
status of the embedded operation by using write status flags. Note that this is a security bit
failure. If the flash memory needs to be secured, the chip should be replaced. When the security
is on, any reads by programming equipment will always return a halfword-length value of
0x0098.
Unsecuring the flash (Enabling read accesses)
To turn off the security feature, write the Auto Security Off command, with the FSE pin set to
V
embedded Security Off algorithm automatically erases and verifies the entire flash array, and
then erases and verifies the security bit.
Any commands written during the embedded operation are ignored. A hardware reset
immediately terminates the embedded operation. In this case, if any erase operation is progress,
data may be corrupted. The FSE pin must be held stable througout the embedded operation.
When an embedded algorithm completes, the flash memory automatically returns to Read
mode.
If any failure occurs during an embedded operation, the flash memory remains locked in
Embedded Operation mode and does not return to Read mode. The system can determine the
status of the embedded operation by using write status flags. If a failure occurs in the memory
array, the security bit is not erased. In this case, the security bit is left on. The chip should be
replaced if a memory array or security bit failure occurs.
The Auto Security Off command erases the flash array prior to turning off the security feature.
Even if a given block is protected, it is unconditionally erased, but the protect status of that
block remains unchanged. The Auto Security Off and Auto Chip Erase command sequences are
the same. The only difference is that the Auto Security Off command requires the FSE pin to be
IH
. After the rising edge of
IH
. In the fourth bus cycle of the command sequence, program 0x0098 at
TMP1940FDBF-80
WE
in the sixth bus cycle of the command sequence, the
WE
in the fourth bus cycle, the embedded Security
TMP1940FDBF