SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 301

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.13 Bus Request and Bus Acknowledge Signals
Note 1:
Note 2:
AD0–AD15
ALE
A0–A23,
BUSRQ
BUSAK
RD , WR
R
CS0 – CS3 ,
Bus float to BUSAK asserted
Bus float after BUSAK negated
/
W
, HWR
If the current bus cycle has not terminated due to wait-state insertion, the TMP1940CYAF does not
respond to BUSRQ until the wait state ends.
This broken lines indicate that output buffers are disabled, not that the signals are at indeterminate
states. The pin holds the last logic value present at that pin before the bus is relinquished. This is
dynamically accomplished through external load capacitances. The equipment manufacturer may
maintain the bus at a predefined state by means of off-chip resistors, but he or she should design,
considering the time (determined by the CR constant) it takes for a signal to reach a desired state. The
on-chip, integrated programmable pullup/pulldown resistors remain active, depending on internal
signal states.
Parameter
Symbol
(Note 1)
t
t
ABA
BAA
TMP1940CYAF-259
t
ABA
Min
0
0
Equation
Max
80
80
Min
0
0
32 MHz
(Note 2)
(Note 2)
TMP1940CYAF
Max
80
80
Unit
ns
ns
t
BAA