SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 234

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4 Operating Modes
13.4.1
Transmit Data Write
Timing
SCLK0 Input
(SCLKS = 0: Rising Edge)
SCLK0 Input
(SCLKS = 1: Falling Edge)
TXD0
INTTX0 Interrupt
Transmit Data Write
Timing
SCLK0 Output
TXD0
INTTX0 Interrupt
Mode 0 (I/O Interface Mode)
which the SCLK clock is driven out from the TMP1940CYAF or input mode in which the SCLK clock
is supplied externally.
(1) Transmit Operations
Mode 0 utilizes a synchronization clock (SCLK), which can be configured for either output mode in
bits of the character is shifted out on the TXD0 pin, and the synchronization clock is driven out
from the SCLK0 pin. When all the bits have been shifted out, the transmit-done interrupt
(INTTX0) is generated.
input is activated. The eight bits of a character in the transmit buffer are shifted out on the TXD0
pin, synchronous to the programmed edge of the SCLK0 input. When all the bits have been
shifted out, the transmit-done interrupt (INTTX0) is generated. The CPU must load the next
character into the transmit buffer by point A.
In SCLK Output mode, each time the CPU writes a character to the transmit buffer, the eight
In SCLK0 Input mode, the CPU must write a character to the transmit buffer before the SCLK0
Figure 13.29 Transmit Operation in I/O Interface Mode (SCLK0 Output Mode)
Figure 13.30 Transmit Operation in I/O Interface Mode (SCLK0 Input Mode)
bit 0
TMP1940CYAF-192
bit 0
bit 1
bit 1
bit 5
bit 6
bit 6
bit 7
TMP1940CYAF
bit 7
A
bit 0
bit 0
bit 1