SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 123

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.
9.1
9.1.1
Chip Select/Wait Controller
variable block sizes, data bus width, wait state insertion, and dummy cycle insertion for back-to-back bus cycles.
These chip select signals are generated when the CPU or on-chip DMAC issues an address within the
programmed ranges. The P40–P43 pins must be configured as CS0 – CS3 by programming the Port A Control
(P4CR) register and the Port 4 Function (P4FC) register.
Address (BMAn) register for each of the four chip select signals, where n is a number from 0 to 3.
consists of a master enable bit, a data bus width bit, a wait state field and a dummy cycle field.
write bus cycles.
The TMP1940CYAF supports direct connections to ROM and SRAM devices.
The TMP1940CYAF provides four programmable chip select signals. Programmable features include
Chip select address ranges are defined in terms of a base address and an address mask. There is a Base/Mask
There is also a set of three Chip Select/Wait Control registers, B01CS, B23CS and BEXCS, each of which
External memory devices can also use the WAIT pin to insert wait states and consequently prolong read and
CS0 – CS3 (multiplexed with P40–P43) are the chip select output pins for the CS0–CS3 address ranges.
Programming Chip Select Ranges
allows one of the chip select output signals ( CS0 – CS3 ) to assert when an address on the address bus falls
within a particular programmed range. The B01CS register defines specific operations for CS0 and CS1 ,
and the B23CS register defines specific operations for CS2 and CS3 (see Section 9.2).
Each of the four chip select address ranges is defined in the BMAn register. The basic chip select model
Base/Mask Address Registers (BMA0–BMA3)
(BAn) field specifies the starting address for a chip select. Any set bit in the address mask field (MAn)
masks the corresponding base address bit. The address mask field determines the block size of a
particular chip select line. The address is compared on every bus cycle.
(1) Base address
(2) Address mask
Note: Use physical addresses in the BMAn registers.
The organizations of the BMAn registers are shown in Figure 9.1 and Figure 9.2. The base address
The address mask field defines the block size of a particular chip select line.
chip select. The lower 16 bits (A15–A0) are assumed to be zero. Thus, the base address is any
multiple of 64 Kbytes starting at 0x0000_0000. Figure 9.3 shows the relationships between starting
addresses and the BMAn values.
masked. Any set bit masks the corresponding base address bit. The address compare logic uses
only the address bits that are not masked (i.e., mask bit cleared to 0) to detect an address match.
Address bits that can be masked (i.e., supported block sizes) differ for the four chip select spaces as
follows:
The base address (BAn) field specifies the upper 16 bits (A31–A16) of the starting address for a
The address mask field defines whether any particular bits of the address should be compared or
CS0 and CS1 spaces:
CS2 and CS3 spaces:
TMP1940CYAF-81
A29–A14
A30–A15
TMP1940CYAF