SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 252

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.14 Software Reset
14.5.15 Serial Bus Interface Data Buffer Register (SBI0DBR)
14.5.16 I
14.5.17 Baud Rate Register 1 (SBI0DBR1)
14.5.18 Baud Rate Register 0 (SBI0BR0)
noise. A software reset is performed by a write of 10 followed by a write of 01 to the SWRST[1:0] field
in the SBI0CR2. After a software reset, all control and status register bits are initialized to their reset
values. Upon resetting the SBI, the SWRST[1:0] field is automatically cleared to 00.
I
causes a START condition to be generated.
I
device, interpreting incoming frame structures as per addressing format. If the ALS bit is set, the SBI
does not recognize a slave address and interprets all frame structures as per free data format.
baud rate generation logic.
TMP1940CYAF is put in IDLE standby mode. This register must be programmed before executing an
instruction for entering a standby mode.
2
2
2
Note:
C bus are done via this register.
C-bus address to which the SBI is to respond.
C Bus Address Register (I2C0AR)
The SBI provides a software reset, which permits recovery from system lockups caused by external
The SBI0DBR is a data buffer interfacing to the I
When the SBI is acting as a master, loading this register with a slave address and a data direction bit
When the SBI is configured as a slave, the SA[6:0] field in the I2C0AR must be loaded with the 7-bit
If the ALS bit in the I2C0AR is cleared, the SBI recognizes a slave address transmitted by the master
Before the I
The I2SBI0 bit in the SBI0BR0 determines whether the SBI is shut down or not when the
A software reset causes the SBI operating mode to switch from I
does not affect the Port A Function register, however.
2
C bus can be used, the P4EN bit in the SBI0BR1 must be set to enable the SBI internal
TMP1940CYAF-210
2
C bus. All read and write operations to/from the
2
C Bus mode to Port mode. This
TMP1940CYAF