SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 170

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.4.2
(3) Using the TMRA0 Match-Detect Output as a Trigger for the TMRA1
16-Bit Interval Timer Mode
16-bit interval timer mode by programming the TA01M[1:0] field in the TA01MOD register to 01.
TMRA0. In this mode, the TA1CLK[1:0] bits in the TA01MOD register are don’t-cares. The clock
input to the TMRA0 can be selected from an external clock and one of three prescalar outputs (see
Table 11.2).
TA1REG. Programming these registers should only be attempted when the timers are not running.
The TMRA0 and the TMRA1 are cascadable to form a 16-bit interval timer. The TMRA01 is put in
In 16-bit interval timer mode, the TMRA1 is clocked by the counter overflow output from the
Write the lower eight bits of a time constant value to the TA0REG and the upper eight bits to the
Example: Generating the INTTA1 interrupt at a 0.2-second interval (fc = 32 MHz)
Example: TA1REG = 04H and TA0REG = 80H
Figure 11.10 Using the TMRA0 Match-Detect Output as a Trigger for the TMRA1
output (TA0TRG) as the clock source for the TMRA1.
TMRA0 clock source, the required time constant value is calculated as follows:
generates a match-detect output, but the TMRA0 continues counting up. A match between the
UC0 and the TA0REG does not cause an INTTA0 interrupt.
generates a match-detect output. When the TMRA0 and TMRA1 match-detect outputs are asserted
simultaneously, both the up-counters (UC0 and UC1) are reset to 00H and an interrupt is
generated on INTTA1. Also, if so enabled, the timer flip-flop (TA1FF) is toggled.
Match-Detect Signal from the
TMRA0 Comparator
Match Output
TMRA0 Up-Counter
(when TA0REG = 5)
TMRA1 Up-Counter
(when TA1REG = 2)
TMRA1 Match Output
Set the TMRA01 in 8-bit interval timer mode. Select the TMRA0 comparator match-detect
Clocking conditions:
Under the above conditions, T16 has a period of 4.0 µs @ 32 MHz. When T16 is used as the
Thus, the TA1REG is to be set to C3H and the TA0REG to 50H.
Every time the up-counter UC0 reaches the value in the TA0REG, the TMRA0 comparator
Every time the up-counter UC1 reaches the value in the TA1REG, the TMRA1 comparator
System clock:
High-speed clock gear: ×1 (fc)
Prescaler clock:
0.2 s
TA1OUT Timer Output
Figure 11.11 Timer Output in 16-Bit Interval Timer Mode
TMRA0 Comparator
Up-Counter Values
INTTA1 Interrupt
4.0 s
(UC1/UC0)
50000
1
TMP1940CYAF-128
0000H
High-speed (fc)
fperiph/4 (fperiph = fsys)
2
C350H
1
3
0080H
4
5
0180H
1
2
0280H
3
2
4
0380H
5
TMP1940CYAF
1
0480H
2
Toggled
1
3