SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 115

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.1
Address Lines
Data Lines
Multiplexed
Address/Data Lines
Pin
Functions
Timing Diagram
Note 1:
Note 2:
Note 3:
8.1.1
8.1.2
Address and Data Buses
Because the data bus is multiplxed with the address bus, even in the C and D configurations, address bits also
appear on the AD bus prior to the data being accepted or provided.
Upon reset, all of Ports 0–2 are configured as general-purpose input ports; programming is required to use them
as address or data bus pins.
Address and data bus configurations are selectable through the programming of the P1CR, P1FC, P2CR and
P2FC registers.
Port 0
Port 1
Port 2
Supported Configurations
A23/A0–A7) pins can be configured as the address and data buses. The TMP1940CYAF supports the
following four bus configurations.
States of the Address Bus During On-Chip Address Accesses
presented. During this time, the address/data bus assumes the high-impedance state.
For external memory interface, Port 0 (AD0–AD7), Port 1 (AD8–AD15/A8–A15) and Port 2 (A16–
While an on-chip address is being accessed, the address bus maintains the previous address externally
A23–8
AD7–0
ALE
RD
24 Max (16 Mbytes)
AD0–AD7
A16–A23
A8–A15
A7–0
A
8
8
A23–8
D7–0
A23–16
AD15–0
ALE
RD
TMP1940CYAF-73
24 Max (16 Mbytes)
AD8–AD15
AD0–AD7
A16–A23
A15
–0
16
16
B
A23–16
D15
–0
A15–0
AD7–0
ALE
RD
16 Max (64 Mbytes)
AD0–AD7
A8–A15
A0–A7
A7–0
C
8
0
(Note 1)
A15–0
D7–0
TMP1940CYAF
A7–0
AD15–0
ALE
RD
8 Max (256 Bytes)
AD8–AD15
AD0–AD7
A0–A7
A15
–0
16
D
0
(Note 1)
A7–0
D15
–0