SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 119

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2.3
ALE (ALESEL
AD[15:0]
ALE (ALESEL
AD[15:0]
ALE Pulse Width
SYSCR3 register within the CG. The default is 1.5 cycles. This setting applies to the whole external
address space.
The ALE pulse width is programmed to 0.5 or 1.5 clock cycles through the ALESEL bit of the
Figure 8.8 shows read cycle timing, with the ALE width programmed to 0.5 and 1.5 clock cycles.
A[23:16]
AD[15:0]
ALE
RD
Figure 8.8 Read Cycle Timing (ALE
0)
1)
ALE = 0. 5 Clock Cycles
tsys
ADR
Upper Address
Figure 8.7 ALE Pulse Width
DATA
TMP1940CYAF-77
tsys
0.5 Clock Cycles
0.5 and 1.5 Clock Cycles)
ADR
ALE = 1. 5 Clock Cycles
Upper Address
1.5 Clock Cycles
DATA
TMP1940CYAF