SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 243

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.4 Description of the Registers Used in I
SBI0CR1
(0x FFFF_F240)
status information for bus access/monitoring.
This section provides a summary of the registers which control I
Name
Read/Write
Reset Value
Function
Note 1: Clear the BC[2:0] field to 000 before switching the operating mode to Clock-Synchronous 8-Bit
Note 2: For details on the SCL bus clock frequency, refer to Section 14.5.3, Serial Clock.
SIO mode.
Number of bits per transfer (Note 1) ACK clock
BC2
7
0
Figure 14.3 I
Serial Bus Interface Control Register 1
BC1
W
6
0
TMP1940CYAF-201
2
C Bus Mode Registers (1)
BC0
5
0
2
C Bus Mode
pulse
0: No ACK
1: ACK
On writes: SCK[2:0] = Internal SCL output clock frequency
000
001
010
011
100
101
110
111
On reads: SWRMON = Software reset monitor
Number of bits per transfer
[2:0]
000
001
010
011
100
101
110
111
BC
0
1
ACK
R/W
4
0
n=4
n=5
n=6
n=7
n=8
n=9
n=10
Software reset operation is in progress.
Software reset operation is not in progress.
# of clock
cycles
8
1
2
3
4
5
6
7
400 kHz
222 kHz
118 kHz
60.6 kHz
30.8 kHz
15.5 kHz
7.78 kHz
Reserved
ACK = 0
3
2
C bus operation and provide I
Data length
Internal SCL output clock frequency
(Note 2) / Software reset monitor
TMP1940CYAF
8
1
2
3
4
5
6
7
SCK2
2
0
Assumptions:
System clock: fc (= 32 MHz)
Clock gear: fc/1
Frequency =
T0 = fperiph/4 (= 8 MHz)
W
# of clock
cycles
SCK1
9
2
3
4
5
6
7
8
1
0
ACK = 1
2
n
T
+
0
4
Data length
SWRMON
(Hz)
SCK0/
R/W
2
8
1
2
3
4
5
6
7
0
1
C bus