SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 217

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write to the Transmit Buffer
Handshaking
input must be low in order for the character to be transmitted. This feature can be used for flow control
to prevent overrun in the receiver. The SC0MOD.CTSE bit enables and disables the CTS operation.
upon completion of the current character until CTS again goes low. If so enabled, the transmit
controller generates the INTTX0 interrupt to notify the CPU that the transmit buffer is empty. After the
CPU loads the next character into the transmit buffer, the transmit controller remains in idle state until it
detects CTS going low.
the RTS pin. The receiving device uses the RTS output to control the CTS input of the transmitting
device. Once the receiving device has received a character, RTS should be set to high in the receive-
done interrupt handler to temporarily stop the transmitting device from sending the next character. This
way, the user can easily implement a two-way handshake protocol.
The SIO0 and SIO1 have the clear-to-send ( CTS ) pin. If the CTS operation is enabled, the CTS
If the CTS pin goes high in the middle of a transmission, the transimit controller stops transmission
Although the SIO0 and SIO1 do not have the RTS pin, any general-purpose port pins can serve as
TXDCLK
Note 1:
Note 2:
SIOCLK
CTS
TXD
(Note 1)
Figure 13.8 Clear-To-Send ( CTS ) Signal Timing
Transmitting Device
TMP1940CYAF
When CTS goes high in the middle of transmission, the transmitter stops transmission
after the current character has been sent.
The transmitter starts tansmission at the first falling edge of the TXDCLK clock after the
CTS signal goes low.
No transmission
takes place during this period.
13
CTS
TXD
Figure 13.7 Handshaking Signals
TMP1940CYAF-175
14
15
(Note 2)
16
1
start bit
2
3
RXD
RTS (Any port)
TMP1940CYAF
Receiving Device
TMP1940CYAF
14
15
16
1
2
bit 0
3