SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 184

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.2.4
Capture Registers (TB0CP0H/L and TB0CP1H/L)
byte-load instructions. When byte-load instructions are used, the low-order byte must be read first,
followed by the high-order byte. The 16-bit capture registers are often simply referred to as TBnCP and
TBnCP1 without the H and L suffix.
The Timer registers are write-only registers and cannot be read.
The capture registers are 16-bit registers used to latch the value of the up-counter (UC0).
Each of the capture registers can be read with either a halfword-load instruction or a series of two
The following diagram shows the addresses of each capture register.
TMRB0
TMRB1
TMRB2
TMRB3
8 high-order bits
8 high-order bits
8 high-order bits
8 high-order bits
0xFFFF_F1A9
0xFFFF_F1B9
0xFFFF_F189
0xFFFF_F199
TB0RG0
TB1RG0
TB2RG0
TB3RG0
8 low-order bits
8 low-order bits
8 low-order bits
8 low-order bits
0xFFFF_F1A8
0xFFFF_F1B8
0xFFFF_F188
0xFFFF_F198
TMP1940CYAF-142
8 high-order bits
8 high-order bits
8 high-order bits
8 high-order bits
0xFFFF_F1AB
0xFFFF_F1BB
0xFFFF_F18B
0xFFFF_F19B
TB0RG1
TB1RG1
TB2RG1
TB3RG1
8 low-order bits
8 low-order bits
8 low-order bits
8 low-order bits
0xFFFF_F18A
0xFFFF_F19A
0xFFFF_F1AA
0xFFFF_F1BA
TMP1940CYAF